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6098 Discussions

how to do "OpenCore Plus evaluation"

Honored Contributor II

when i see the doc of FIR ip core(it comes from the ip7.1 which i download it from website of altera ), and i try to follow the steps of it , now the system has .sof already ,but i dont know how to do next ,how to know whether it really works ,, 


Program a 


After you have compiled your design, program your targeted Altera 

device and verify your design in hardware. 

With Altera's free OpenCore Plus evaluation feature, you can evaluate the 

FIR Compiler MegaCore function before you purchase a license. 

OpenCore Plus evaluation allows you to generate an IP functional 

simulation model and produce a time-limited programming file. 

You can simulate the FIR Compiler MegaCore function in your design 

and perform a time-limited evaluation of your design in hardware. 


Set Up Licensing You need to purchase a license for the FIR Compiler only when you are 

completely satisfied with its functionality and performance and want to 

take your design to production. 



can you tell me what is the detail step that i need to do next. sorry i am a new ,so patiently help me:confused:
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2 Replies
Honored Contributor II



I think that the issue is more in understanding what all these words are trying to tell you because you are new. I have been watching your progress all along and you are moving in the right direction. 


Altera and others make IP that you can use that is delivered through the MegaWizard. 

Some of that IP is free to use with no license. Some is made available with a chunk of internal code that makes the IP stop working if the JTAG download cable is not connected to the PC or after an internal timer expires. If you like it, then you buy a license and those restrictions are removed. I think you get that part. 


What I sense is not clear to you is the following; 

"now the system has .sof already, but i dont know how to do next, how to know whether it really works. ... can you tell me what is the detail step that i need to do next. sorry i am a new, so patiently help me." 


... (You can simulate the FIR Compiler MegaCore function in your design...) 

In order to verify that the desired IP is doing what you wish, initially you can simulate the design, and 'If' you can create proper stimulation on the inputs of the design, and 'if' you know what you expect the output of the design to do, you might be able to tell if the 'stuff in the middle' (your design with the IP in it) is performing as expected. [Build little pieces - test them, and add more]. 


... (and perform a time-limited evaluation of your design in hardware.) 

OK, so the next step is JTAGing the .sof file onto your board and testing it. What exactly does that mean? 


In order to verify in hardware, you need the board, and you also need a way to drive into (onto) the board signals that will be typical of the signals that your board will be expected to be 'processing' through the FPGA (IP) design. Let's say you have a board that has an A/D convertor on it (the board) that then feeds into an FPGA which is doing some filtering of the sampled signals, you will need to provide input into the A/D inputs. If the IP Filter design is doing low pass or high pass filtering as an example, you could feed the output of an MP3 player into the A/D, and then filter the audio, and send it out other pins to a D/A and listen as you adjust the cutoff frequency. You might even design a dynamic Filter so that the co-efficents can be changed by writing values into internal RAM in the FPGA, then using Signal Tap (via the JTAG cable) to dynamically change the memory values. This would then change the response of the filter and you could hear the changes. 


All this and more is what is meant be the statement ... (and perform a time-limited evaluation of your design in hardware.) 


Does this help out? 

Honored Contributor II

yes . thank you very much ,and it does work, i think FPGA is very interesting, under so many warm-hearted help , believe i can know more about it as soon as possible:)