FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

how to increase the depth of dcfifo more than 131000 words ?

Altera_Forum
Honored Contributor II
1,046 Views

Hi, 

 

Does anyone know how to increase the depth of dcfifo to more than 131000 words ? The maximum selectable from Megacore is 131,000 something... 

 

connecting two of these together? 

 

regards, 

Michael
0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
85 Views

Why do You need such a big FIFO? This is maximum available. Either do Your own FIFO using RAM or use external FIFO chip.

Altera_Forum
Honored Contributor II
85 Views

Connecting a DCFIFO and a SCFIFO back-to-back is very easy. This would allow you to double the size. 

 

I'm not sure whether 'directly' instantiating the fifo in your code (use the MegaWizard generated code to see how to do this) would allow any size fifo, but the .pdf doc looks like this would work ok.
Altera_Forum
Honored Contributor II
85 Views

 

--- Quote Start ---  

Why do You need such a big FIFO? This is maximum available. Either do Your own FIFO using RAM or use external FIFO chip. 

--- Quote End ---  

 

 

 

To keep a large chunk of data given from ADC, generally i want a FIFO to be as big as possible. now i want to build a DCFIFO based on SRAM(2MB). Any ideas how? 

 

Thank you. 

 

regards, 

Michael
Altera_Forum
Honored Contributor II
85 Views

Write to Your FIFO and count words. Remember the last address You've written and begin read from there backwards. Simple as that :)

Altera_Forum
Honored Contributor II
85 Views

 

--- Quote Start ---  

Write to Your FIFO and count words. Remember the last address You've written and begin read from there backwards. Simple as that :) 

--- Quote End ---  

 

 

Isn't that a LiFo (last in, first out) then?
Altera_Forum
Honored Contributor II
85 Views

My bad, begin from the place You've started writing :)

Altera_Forum
Honored Contributor II
85 Views

Using up all the on chip RAM when you have external RAM seems like a waste of resources. Just build an ADC interface that supports Avalon-ST, hook it up to a clock crossing FIFO if need, then hook up the FIFO/ADC to a DMA and push it into memory. Also long as you have enough memory bandwidth and you feed the DMA descriptors fast enough you should never drop samples.

Reply