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I designed a image capture IP with FIFO and DMA. I don't know how to desige the host port to launch the DMA which transfer the data from FIFO to sdram. I don't know how to relate the host port with DMA.
Thanks very much!Link Copied
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I'm sorry I can't see the links due to my low posts.
But I want design it myself.Also the exiting ip is not suit for earlier device such as cyclone.- Mark as New
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hi,skw2xx
what is the meaning of host port ,cpu?- Mark as New
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I am sorry. Actully,I mean the Avalon Memory-Mapped Master port.
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--- Quote Start --- I am sorry. Actully,I mean the Avalon Memory-Mapped Master port. --- Quote End --- in my opinion,DMA transfer is lauched by CPU,FPGA is slave,only receive DMA command and response.
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