I designed a image capture IP with FIFO and DMA. I don't know how to desige the host port to launch the DMA which transfer the data from FIFO to sdram. I don't know how to relate the host port with DMA.Thanks very much!
--- Quote Start --- I am sorry. Actully,I mean the Avalon Memory-Mapped Master port. --- Quote End --- in my opinion,DMA transfer is lauched by CPU,FPGA is slave,only receive DMA command and response.