FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5920 Discussions

how to use external pll for altlvds_tx cyclone iv

Altera_Forum
Honored Contributor II
844 Views

i need to interface a lcd driver device with a FPGA throught LVDS port. the FPGA is cyclone iv EP4CE30F23, it used as lvds transmitter . the lcd driver device has lvds interface, it used as lvds receiver. In receiver, the lvds receiver timing diagram is showed in pic1 . For example , the FPGA transfer 7 data via one lvds channel , so the lvds channel number is 1, the deserializtion factor is 7. when the lvds out data rate is 70Mbps , the output clock rate is 10MHz. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12799&stc=1  

my questions: 

[1] How can i use altlvds_tx ip core generate waves like pic1 ? 

[2] when i use internal pll for altlvds_tx , i find the range of phase alignment between tx_outclock and tx_out is from 0 to 51 degree, it can't meet the requirements of pic1. how can i resolve this question ? 

[3] when i use external pll for altlvds_tx , i find that it can adjust phase alignment between tx_outclock and tx_out , but i don't know how to calculate the phase . i use altpll ip core generate fast clock and slow clock , but how to calculate the phase of fast clock and slow clock ? when use external pll for altlvds_tx , it must use tx_syncclock , how to calculate the phase of it? 

 

Thank you for your help! 

 

Leo
0 Kudos
0 Replies
Reply