FPGA Intellectual Property
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intel_agilex

sumanth1
Novice
488 Views

 Hi,

 

I am using E-tile Ethernet IP for Agilex to configure 10G_Base-T Ethernet PHY. But in that E-Tile Ethernet IP there is no provision for MDIO and MDC pins from IP. So I have used Ethernet MDIO core IP. To Access external PHY MDIO ,MDC pins required . I have given below design for reference. please suggest me any reference example design for external PHY access  by using Ethernet MDIO core IP and ethernet IP individually. 

sumanth1_0-1675425080509.png

 

And also, please share any application code example for MDIO and MDC register accessing through eclipse nios processor.

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Regards,

Sumanth Raju

3 Replies
ZiYing_Intel
Employee
433 Views

Hi Sumanth Raju,


Thanks for submitting the issue. Please do allow me have some time to look into your issue and I will get back to you with findings.


Best regards,

Zi Ying


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ZiYing_Intel
Employee
426 Views

Hi Sumanth Raju,

 

Based on my current knowledge, I know that MDIO IP core can be used:

 

  1. Intel FPGA 10-Gbps Ethernet MAC (support up to 10G)

https://www.intel.com/content/www/us/en/docs/programmable/683426/18-1-18-1/about-ll-ethernet-10g-mac.html

  1. Intel FPGA Triple Speed Ethernet IP Core (support up to 1G)

https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/about-this-ip.html

 

Currently we can't provide the reference design example with public due to the confidential of company.

 

Best regards,

Zi Ying

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ZiYing_Intel
Employee
396 Views

Hi Sumanth Raju,


Since I have addressed your question and haven't hear any feedback from you, I am now close the case. If you have any question after the case closed, please do feel free to submit another issue.


Best regards,

Zi Ying


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