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Altera_Forum
Honored Contributor I
1,290 Views

mSGDMA & NicheStack

Hi, 

 

with Quartus Prime Altera has added the mSGDMA IP core to Qsys (in Pro version it is the only DMA core available). However there has long been an mSGDMA IP on alterawiki and I am not sure to what extent the two resemble. This name conflict makes information search on internet even more complicated... 

 

My system starts the NicheStack, intializes succesfully (at least reported as succesful to STDOUT) but the RX_SGMDA never seems to accept data from the MAC (I can see with SignalTap that MAC backpressure is ON, PCS received correct frame data in buffers but no transfer to main memory is completed). My guts tell me it has to do with the descriptors. I assume it can be either: 

- wrong QSYS wiring (there is no reference design using this new core - only a few designs using the sub-core units) - but this is unlikely, the wiring seems intuitive 

- wrong software configuration (MAC profile wrong?) 

- NicheStack bug (support added recently with Q17.0) 

 

What I do: 

qsys (see attachment) 

- no external descriptor memory instantiated 

- connected the AvlMM master (mm_write) to main memory 

- all AvlMM slaves (descriptor slave, response, csr) --> cpu.data_master 

 

bsp 

- compilation with set_setting hal.make.bsp_cflags_defined_symbols "-DTSE_MY_SYSTEM" 

- tse_my_system.c declaring 

alt_tse_system_info tse_mac_device = { TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO(TSE_MAC, 0, TX_MSGDMA, RX_MSGDMA, TSE_PHY_AUTO_ADDRESS, 0) };  

 

Has anyone experience with this IP? Can anyone give a hint what I do wrong? 

 

Thank you!
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Altera_Forum
Honored Contributor I
177 Views

I solved it. 

The problem was in my design: "Enable the Pre-Fetching module" option was not checked in my mSGDMA component. When activated the component interface was similar to that of the older SGDMA core. 

What I find disturbing is that the tse driver does not check for it.
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