- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hello ,
In the Embedded Peripherals IP User Guide under msgdma maximum transfer length , it is mentioned that "With shorter length width being configured, the faster frequency of
mSGDMA can operate in FPGA".
What is the reason behind this comment?
Is it related to the FPGA implementation or is it related to the transfer rate(not to keep the bus busy for longer time)?
Is there any comparison results for the different "Transfer Length" during the mSGDMA transfer?
is there any best value for the Transfer Length?
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Using smaller length improves the frequency of the mSGDMA,
The maximum transfer length is the maximum number of bytes transferred by each descriptor.
We do not have the comparison numbers and best values.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thank you for your valuable response.
"Using smaller length improves the frequency of the mSGDMA, "
I wish to understand a bit more about the above statement. Can you please elaborate?
just for my understanding...Increasing in frequency means increase in throughput? is that you mean?
what is actually confusing me is as you mentioned there is no transfer length comparison results available to compare the throughput .
please correct me if I am wrong.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Increasing in frequency will result higher performance, not higher throughput.

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page