My situation is such that I have to transfer data precalculated by the SoC ARM CPU (Arria 10, Cyclone V) to the FPGA. My strategy is to use an mSGDMA read master component in the FPGA with MM port connected to the F2SDRAM bridge and a Avalon ST port to transmit the data to FPGA soft IP. So far so good. In the application it happens that data precalculated by the CPU has to be processed by the FPGA several times. I see the following options: 1) Store the data N times in SDRAM and provide one “big” descriptor to the mSGDMA => this may consume a lot of memory 2) Store the data only once to SDRAM and provide N descriptors targeting the same address range to the SGDMA => less memory consumption but for short memory ranges to be repeated the descriptor write overhead is significant 3) Store the data only once to SDRAM as before but provide only one descriptor to the mSGDMA and advice the mSGDMA to “reuse” or “process” the descriptor N times My question is if there is a possibility to implement 3) somehow. I did not find a solution yet. There seem to be options to repeat one descriptor until infinity but I am missing an option to define a fixed number of repetitions. Is there a ready-made option I have overlooked? Of course there is the option to write a special prefetcher to implement such a scenario. Thanks a lot in advance for any answers!