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Altera_Forum
Honored Contributor I
729 Views

master write done signal high on startup

Hi, I designed a Verilog unit which interacts with the SDRAM by means of two Avalon MM Master Templates (which I just abruptly downloaded and added to my Sopc builder Nios System after adjusting my component interface to match the user and control side of the template) and with my processor by means of a MM Slave Template. My problem is: I can successfully post data from Nios to component with the slave, but as soon as I program my device with the altera programmer (I am using a DE1 and I connected some of the control outputs to the LEDS for debugging) the control_write_done and control_read_data_available signals are instantly high (and obviously I haven't issued any control_read_go or write_go signal). I have tried also by connecting to the clock's reset the reset ports of the two Masters. 

 

Ps. I attach the SoPC Builder diagram and the schematic of the connections with my Coprocessor
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Altera_Forum
Honored Contributor I
32 Views

I think the reset ports should be connected. How are those signals generated in your code?

Altera_Forum
Honored Contributor I
32 Views

the reset_n port is connected to one of the DE1 pushbuttons, but I didn't connect the ports inside of SoPC Builder because if I do I get a warning about some "global reset" that makes the connection redundant.

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