p-tile transactions pending bit in device status register

[Daphn]

Hi there,

Who, hard IP or end user, should take care of transactions pending bit in device status register in p-tile?

Thanks in advance.

Daphn

[ZiYing_Intel]

Hi Daphn,

Thanks for submitting the issue. Please do let me have some time to investigate on it and I will be get back to you with findings.

Best regards,

Zi Ying

[ZiYing_Intel · Accepted solution]

Hi Daphn,

In my opinion, I think that both need take care the transaction pending bit in the device status register. The user application need to specify the configuration register that they need to use. Besides that, the power management software must ensure that all outstanding non-posted requests have received their associated completion.

In the Section 4.9 P-tile PCLe IP User guide, it show that how important the Power Management Interface related to the transaction pending bit in device status register,

https://www.intel.com/content/www/us/en/docs/programmable/683059/22-3-8-3-0/power-management-interface-21779.html

Best regards,

Zi Ying

[ZiYing_Intel]

Hi Daphn,

I wish to follow up your case.

Do you have any questions about this matter?

Else I would like to have your permission to close the case.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi Daphn,

Since the case has been idling without further inquiries and it is not recommended to idle the case for a longer time, I will set this case as close case as the solution was provided.

Please do feel free to open another case and submit the questions once you found that you have another inquiries.

Best regards,

Zi Ying