FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5984 Discussions

pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv segfault?

Honored Contributor II

Start time: 17:39:56 on Dec 15,2017vlog pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 ** Fatal: Unexpected signal: 11. ** Error: pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv(12): in protected region End time: 17:39:56 on Dec 15,2017, Elapsed time: 0:00:00  


Did anybody experience this with modelsim ase in 17.1?
0 Replies