sir,now i am doing a project with pci express based and choose the cyclone 4 gx epc4gx75 i already generated files using avlon st megawizard interface .now i choose EXAMPLE_CHAINING_DMA.VHD as my top level entity as my pcie link side (means connector side signals ). is it right or not ? but to interface at application layer(user application side) which vhd file i have to choose and from where i have to start access with pcilink to user application side and also reset signals and clock signals i am confusing can anyone guide me in a right direction!
You may refer to Cyclone IV GX pcie example design at this link, follow the reset and clocking in the example design.https://www.altera.com/support/support-resources/software/download/refdesigns/ip/interface/dnl-pciex... To be more easier, just port over this example design to target your FPGA part number cyclone 4 gx epc4gx75. .