FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

phylite ip simulation: i am getting the correct output in the io signal of phylit ip but in output line the data is mismatching. can any one help

AC1
Beginner
‎11-30-2018 09:25 AM
1,946 Views
 
0 Kudos

Link Copied

2 Replies
MuhammadAr_U_Intel
Employee
‎12-03-2018 08:46 AM
960 Views

Hi,

Could you explain the issue in a bit more details.

 

Please provide some waveform captures to demonstrate the issue and attach a small testcase to replicate the issue ?

 

Thanks,

Arslan

 

0 Kudos
Copy link
MuhammadAr_U_Intel
Employee
‎01-04-2019 01:33 AM
960 Views

We are working on this with user in private message Looking at the specific case, this sound like due to incorrect PhyLite IP settings.

 

In case anyone else come across same issue, please try simulating the example design first and then compare the waveform with user specific case.

 

Thanks,

Arslan

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.