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Altera_Forum
Honored Contributor I
925 Views

problem of LCD controller

hi, 

 

i would convert a verilog code to vhdl code , 

 

//code verilog  

always@(posedge iCLK or negedge iRST_N) 

begin 

if(!iRST_N) 

begin 

LUT_INDEX <= 0; 

mLCD_ST <= 0; 

mDLY <= 0; 

mLCD_Start <= 0; 

mLCD_DATA <= 0; 

mLCD_RS <= 0; 

end 

else 

begin 

........ 

----------------------------------------------------------------------- 

--vhdl code 

process(iCLK,iRST_N) 

variable var_mDLY : std_logic_vector(17 downto 0); 

begin 

 

if (( iCLK 'event and iCLK='1') or (iRST_N 'event and iRST_N='0')) then 

if(iRST_N='0') then  

LUT_INDEX <=(others =>'0'); 

mLCD_ST <=(others =>'0'); 

mDLY <=(others =>'0'); 

mLCD_Start <='0'; 

mLCD_DATA <=(others =>'0'); 

mLCD_RS <='0'; 

 

else 

............ 

 

when i compile this error appear: 

 

Error (10628): VHDL error at LCD_TEST.vhd(61): can't implement register for two clock edges combined with a binary operator 

 

 

 

so if somebody have any solution ? 

 

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4 Replies
Altera_Forum
Honored Contributor I
49 Views

The Verilog always block can't be translated line by line, the syntax for a synchronous process with asynchronous reset is somewhat different. In my opinion, it's more intuitive than the respective Verilog construct that uses the negedge keyword for a level sensitive condition. You can use the language templates in Quartus editor context menu to look up the correct VHDL syntax for common design constructs.  

process(iCLK,iRST_N) variable var_mDLY : std_logic_vector(17 downto 0); begin if iRST_N='0' then LUT_INDEX <=(others =>'0'); mLCD_ST <=(others =>'0'); mDLY <=(others =>'0'); mLCD_Start <='0'; mLCD_DATA <=(others =>'0'); mLCD_RS <='0'; elsif iCLK 'event and iCLK='1' then -- you can also write rising_edge(iCLK) end if; end process;
Altera_Forum
Honored Contributor I
49 Views

thank's for your reply 

 

the code compile correctly but there is no result in the LCD. 

 

because i would to creat a controller of LCD 16x2 in DE2 

 

i don't know what the origine of problem ? may be this part of initilization of 

 

LCD.  

 

but i would to ask you i can't add the falling_edge(iRST_N)? 

 

because the verilog code he use 

 

always@(posedge iCLK or negedge iRST_N) 

begin 

if(!iRST_N) 

begin
Altera_Forum
Honored Contributor I
49 Views

As I said, negedge doesn't actually mean an edge sensitive condition in this place. VHDL is more exact in this respect. 

 

There may be many reasons why the LCD controller code is not working. You didn't show the relevant parts of it. If you have a known working Verilog controller code, you don't need to translate it to VHDL. You can instantiate it as a component in your VHDL design
Altera_Forum
Honored Contributor I
49 Views

Thank you very much  

 

i try a whole code and i use some component in verilog, after that i found 

 

the mistakes in my code. 

 

i would know if you have any idea for create a master who can read/write in LCD ,i try with this code i compiled with no error but  

no result in the LCD 

 

you can See both attached files
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