problem with FIR IP

[Altera_Forum]

FIR IP filter output waveform shake up and down ,  

 Input signal contains the useful signal and the noise signals ,   so the frequency of the noise signal may be greater than half of the sampling frequency of the filter ,   what I want from the output of the FIR IP filter is just the useful signal ,  so should the the sampling frequency of the filter must ust be much greater than twice the frequency of all input signal include the noise signal ???  and why FIR IP filter output waveform shake up and down ???  Looking for your helping reply , thank you very much !!!

[Altera_Forum]

--- Quote Start ---  FIR IP filter output waveform shake up and down ,   Input signal contains the useful signal and the noise signals  --- Quote End ---    are you referring to analogue signal passed through an ADC?  Once a signal is sampled into digital domain then the frequency range of digital domain is 0 ~ Nyquist and anything more than Nyquist would have already aliased unless there was anti alias filter. Your FIR should pass the signal and remove noise from edge of signal to Nyquist and it should be sampling at ADC rate.

[Altera_Forum]

--- Quote Start ---  are you referring to analogue signal passed through an ADC?  Once a signal is sampled into digital domain then the frequency range of digital domain is 0 ~ Nyquist and anything more than Nyquist would have already aliased unless there was anti alias filter. Your FIR should pass the signal and remove noise from edge of signal to Nyquist and it should be sampling at ADC rate.  --- Quote End ---    Analogue Signal which passed through the ADC into the FPGA is High frequency and Weak amplitude&#65292;  so the ADC rate is required high frequency ,  but in FPGA , through processing &#65288;digital lock-in amplifier&#65289; &#65292;then I need a low-pass FIR filter , so the sampling frequency can't be set too high ,  then the output waveform of the FIR shake up and down .  for example :  1. set the FIR parameter : Fs=1KHZ , Fc=50HZ(Fs < 2*input signal) input signal &#65306; 1KHZ+1HZ output signal : 1HZ but the output signal waveform shake up and down , seems like there are some other low frequency signal !  2. set the FIR parameter : Fs=5KHZ , Fc=200HZ (Fs > 2*input signal) input signal &#65306; 1KHZ+1HZ output signal : 1HZ but the output signal waveform is normal and don't shake .   I’m confused , looking for your reply and thanks a lot !

[Altera_Forum]

So you have two single tones coming from ADC; one at 1Hz, and one at 1KHz and you want to filter off the 1Khz and pass the 1 Hz 

You haven't said anything about Fs of signal itself. You have chosen Fs of 1KHz first then FS of 5KHz. You can't just pick a value. Your Fs must be that of input signal and should be same as ADC Fs unless you have done downsampling which I doubt.

[Altera_Forum]

--- Quote Start ---  So you have two single tones coming from ADC; one at 1Hz, and one at 1KHz and you want to filter off the 1Khz and pass the 1 Hz You haven't said anything about Fs of signal itself. You have chosen Fs of 1KHz first then FS of 5KHz. You can't just pick a value. Your Fs must be that of input signal and should be same as ADC Fs unless you have done downsampling which I doubt.  --- Quote End ---    The Fs of signal itself is 25MHZ .  This example is for testing the function of the FIR IP filter , and I want to know how to make a low-pass FIR IP filter with high sampling frequency signal ?  thanks a lot !!!

[Altera_Forum]

so your fir filter must work at 25MHz and filter off the 1 KHz tone i.e. a cutoff ratio of 1/25000. Very tough and not practical in FPGAs

[Altera_Forum]

Can you describe the signal you are sampling (its amplitude and frequency), and the ADC you are using? Sampling at 25MHz seems like too much oversampling.

[Altera_Forum]

--- Quote Start ---  Can you describe the signal you are sampling (its amplitude and frequency), and the ADC you are using? Sampling at 25MHz seems like too much oversampling.  --- Quote End ---    In the designed system , 100KHZ and 200KHZ signals are sampled by ADC through 25MHZ sampling rate &#65288; its amplitude is MV level &#65289;, by system processing , FIR IP filter final input includes a DC signal(which is generated after system processing) and three high-frequency signal(100KHZ , 200KHZ ,300KHZ) and maybe some high frequency noise signal.  what I want is only the DC signal , so I'm confused how to set the FIR IP filter's parameter ( Fs and Fc ) ???  thank you very much for your reply !

[Altera_Forum]

You better try IIR filter such as the leaky integrator where: 

 y(n) = alpha*y(n-1) + (1-alpha)*x(n);  alpha from 0 ~ <1 to control cutoff point.