problems of initiate 10/100/1000mac wtih 1000 base -x/sgmii

[Altera_Forum]

hi, 

hello everyone, now i'm debug a ethernet ip in stratixiigx kits, when i generate the ip core,i find the address ie 8 bit width,but it's user guide says the max address of mac control interface is 0x3FC,the 8 bit data can demonstrate the 0x3FC?why?  another problem is when i use 100M ethernet,my system clock is 100MHz,it gernate the clk,ff_tx_clk,ff_rx_clk,I think the clk is 100MHz,but how can i config the ff_tx_clk,ff_rx_clk?  expect someone help me,thankful

[Altera_Forum]

The address bus on an Avalon slave directly designates a register number. As the data bus is 32-bits wide, the address is shifted by two bits. Ie when you put 0x10 on the address bus, you are in fact accessing the register at address 0x40.

[Altera_Forum]

hi,i find you are more knowledgeable,you help to resolve many problems with ethernet ip core,thanks