quartus 19.4 can not use more than 2 clocked video output II IP at one project?

[LZhi01]

hello,when i use 2 clocked video output II IP,one is separate mode  for HDMI interface,one is embedded mode for SDI interface,but the project can not compiled successfull. The quartus(version 194) reports the following error "Error(13305): Verilog HDL error at vout4_alt_vip_cl_cvo_2010_4ugwp2y.v(778): can't find port "sdi_cvo_rden" " how can i resolve this problem?

[Deshi_Intel]

Hi,

1. May I know is this Quartus synthesis error or fitter error ?
2. Also have you traced the design files as indicated in the error message, is the error coming from CVO IP used to interact with HDMI IP or SDI IP ?

I checked VIP user guide on the usage of sdi_cvo_rden.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_vip.pdf
• Have you enabled this port correctly as shown in (page 79, table 31) and also connect the port correctly as shown in (page 29, figure 14) ?

Thanks.

Regards,

dlim

[LZhi01]

i used two CVO IP, one with embedded mode (sdi_rden connect to sdi ii ip interface);one with separate mode (without sdi_rden but hsync,vsync connect ot HDMI IP interface); the error is coming from vout4 IP which is connected to sdi ip.

[Deshi_Intel]

Hi,

Thanks for sharing the error screen shot. So, we are dealing with synthesis compilation design error here.

The error message looks like is complaining about design syntax error that's likely induced by user error

• I presume you are generating 2 separate VCO IP that have different setting insides.
• Also, my advice to you is pls check to ensure you enabled sdi_cvo_rden port correctly as shown in (page 79, table 31) and also connect the port correctly as shown in (page 29, figure 14) ?
• Else if you can share your design archived QAR file with me then I can help to review your design connection.

Thanks.

Regards,

dlim

[LZhi01]

please help me to check the project below.​thank you very much.

[LZhi01]

hi,DeshiL_Intel,did you reviewed my project? i am looking forward to receiving your reply, thank you very much.

[Deshi_Intel]

Hi,

Yes, I am reviewing and debugging your project.

This issue looks like missing "sdi_cvo_rden" port generation in CVO IP. I can see that you already enable "embedded in video" option in CVO IP.

I plan to try out few more debug from my end but if still failed then I will file investigation report to CVO IP developer to look into issue.

Will keep you posted on issue status update.

Thanks.

Regards,

Deshi

[LZhi01]

hi,thank your reply;also,i make some more tests.

1、i just make a project with only one cvo ip(no matter embedded mode or separate mode),all is well;

2、i first add one cvo ip with embedded mode,then add another cvo ip with separate mode, the project can compile but have warring (13410): Pin "vout_hdmi_clocked_video_vid_datavalid[0]" is stuck at GND. With siganl tap ii file,all the cvo (separate) signals are low.

3、i first add one cvo ip with separate mode,then add another cvo ip with embedded mode,the project can not compile with error "Error(13305): Verilog HDL error at vout_sdi_alt_vip_cl_cvo_191_6gvqwty.v(661): can't find port "sdi_cvo_rden" .

[Deshi_Intel]

Hi,

Thanks for additional input.

I tested with latest Quartus v20.1 but still failed.

I have filed issue investigation report to Intel VIP Engineering team to look into issue.

Stay tune for update.

Thanks.

Regards,

dlim

[Deshi_Intel]

Hi,

Intel Engineering team has feedback this indeed is a bug in CVO IP.

They are working to fix CVO IP core design now and targeted to release the issue fixed CVO IP in next Quartus release version which is v20.2 in around early July.

Thanks.

Regards,

dlim

[Deshi_Intel]

Hi,

Kindly bear for the fix release while you work on other stuff in your project development first.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim