question about “ A10SOC as PCIE RC ”

[JET60200]

hello expert,

We plan to start an “ A10SOC PCIE RC” design,  while the peer side  PCIe EP is a "pcie subcard w/ (gen3x8)".   Our target is to run Linux System on this A10SOC （HPS）,  and  use HPS ARM core to communicate with the PCIe EP  slave device.  A few question I'm not clear :

1)   to my understanding,  A10 FPGA‘s HIP could work as RC , to communicate with an external " EP Device",  is it correct ?     Thus my question is "How  could  A10SOC HPS（ARM  communicate to that external PCIE EP device directly ?" ,  to execute some heavy-loading data moving ,  such as Cypro Accelator or Encoding/Decoding  ?   

we must ensure the throughput and data bandwidth is sufficient between  HPS and external PCIe EP device.  isthere any suggestion or reference design example ?  

sth like below:

Arria10 SOC(RC)   to  PCIe EP  ( Crypto card ) ：
----------------------------                  ----------------
|                        |                  |                  |                        |
|                        |                  |                  |                        |
|                        |    FPGA    |   HIP        |   EP device   |
|       HPS         |                  |<<===>> |                       |
|                        |                  |                  |                        |
|                        |                  |                  |                        |
--------------- -------------                   ----------------

Thanks a lot

[Deshi_Intel]

Hi,

It's possible to use Arria 10 PCIe HIP as root complex but the reference design for it is limited as typically we promote FPGA for PCIe EndPoint application.

So far I can only find below A10 PCIe RC reference design using HPS but it's targeting till PCIe Gen2 x8 only.

Nevertheless, fell free to check it out.

• https://rocketboards.org/foswiki/Projects/A10AVCVPCIeRootPortWithMSILTS

Thanks.

Regards,

dlim

[JET60200]

Thanks @Deshi_Intel  for quick response , Will check the details

best regards

[Deshi_Intel]

Alright. Good luck in your project development.