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Hi all.
I'm struggeling with a problem trying to write some datas into a DCFIFO.
The write signal (wrreq) is an output from a fsm like this:
......
p_fifo_wr_fsm : process(wrclk, RST)
begin
if (RST = '1') then
wr_fifo_fsm_st <= ST_IDLE;
data <= '0';
wrreq <= '0';
elsif rising_edge(wrclk) then
if (ENABLE = '0') then
wr_fifo_fsm_st <= ST_IDLE;
data <= '0';
wrreq <= '0';
else
case wr_fifo_fsm_st is
when ST_IDLE =>
if ((IN1 = '1') AND (IN2 = '1'))then
wr_fifo_fsm_st <= ST_WR;
data <= DATAIN;
wrreq <= '1';
else
wr_fifo_fsm_st <= ST_IDLE;
data <= '0';
wrreq <= '0';
end if;
......
The problem is: the first data written into the fifo is missing when I try to read it.
The first read report the second written data.
The fifo is "no show ahead".
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Hi,
Could you share the design QAR file, simulation result and testbench for investigation? To generate the QAR file, click on Project > Archive Project.
Thanks
Best regards,
KhaiY
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Hi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Best regards,
KhaiY

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