rx_locktodata and rx_locktorefclk

[Altera_Forum]

I have a problem whit the Clock Recovery Unit. 

I'm using the Serial RapidIO protocol through ALT2GXB megafunction.  I tried to train the CRU by asserting the rx_locktorefclk at a certain frequency (for example 125MHz to rx_cruclk clock).  After this, i switch from lock-to-reference to lock-to-data asserting rx_locktodata (and optionally de-asserting rx_locktorefclk).  To rx_datain port, i send 2-byte-encoded (i.e. 20 bits/clock cycle, at 2,5GHz frequency). Thanks to the encoder 8b10b, rx_datain port reads 6 "ones" and 6 "zeros" during a clock cycle.  The problem is that the CRU PLL continues to operate in lock-to-reference mode. In fact, if i change the frequency at rx_cruclk port, the rx_clkout follows it!

[Altera_Forum]

I think what you're really saying is that the CRU is not able to lock to the incoming data stream. Is that correct? 

 Jake

[Altera_Forum]

Yes, i expect that the transceiver will continue to work at the same frequency (125MHz) when swithing from lock-to-reference to lock-to-data, because the data are serialized (16 parallel bits to 1 bit) at this frequency (125MHZ before serialization, 2,5GHz after 8b10b encoding). 

 What i really want is to communicate 2 fpga with only one cable, the data one! I want that the receiver fpga recover the clock signal from data (8b10b encoded).  How i can do it?

[Altera_Forum]

did you found the solution?