rx_pma_clk to rx_clkout setup timing viloation in the phy of LL10G_10GBASER_RegMode

[Altera_Forum]

Hi 

I genearate the LL10G_10GBASER_RegMode example design. then use the mac and phy in my project, but I found it often reports timing viloation between below clock domains in the PHY low_latency_baser. Did you have any ideas about how to fix this timing violation in low_latency_baser.  altera_eth_10g_mac_base_r_low_latency_wrap|baser_inst|xcvr_native_a10_0|rx_pma_clk between altera_eth_10g_mac_base_r_low_latency_wrap|baser_inst|xcvr_native_a10_0|rx_clkout

[Altera_Forum]

Here are the pins in my project, 

[0][1] share the ref_clk_clk1 [2][3] share the ref_clk_clk2  # Bank GXBL1E set_location_assignment PIN_AN42 -to tx_serial_data[0] set_location_assignment PIN_AM44 -to tx_serial_data[1] # Bank GXBL1H set_location_assignment PIN_R42 -to tx_serial_data[2] set_location_assignment PIN_P44 -to tx_serial_data[3]   # Bank GXBL1E set_location_assignment PIN_AN38 -to rx_serial_data[0] set_location_assignment PIN_AM40 -to rx_serial_data[1] # Bank GXBL1H set_location_assignment PIN_R38 -to rx_serial_data[2] set_location_assignment PIN_P40 -to rx_serial_data[3]  # refclkgxb* Settings - LVDS # 322.265625MHz set_location_assignment PIN_AH36 -to ref_clk_clk_1 set_instance_assignment -name IO_STANDARD LVDS -to ref_clk_clk_1 set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to ref_clk_clk_1  set_location_assignment PIN_T36 -to ref_clk_clk_2 set_instance_assignment -name IO_STANDARD LVDS -to ref_clk_clk_2 set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to ref_clk_clk_2

[Altera_Forum]

Jackieyes, 

 I don't know if I can help, but I'll throw out an idea and ask for some help in return.  I notice that the timing violation is between two different clock domains, as you mention. Sometimes it's okay for there to be what seems to be a violation between different clock domains, but the timing analyzer does not know that it's okay. Perhaps you have to tell the timing analyzer that it is okay for there to be a violation. You can do this by going to the timing analyzer Constraints menu and setting Set False Paths between the two clocks. Use the full clock names (they're long and weird) as they appear in your error messages. If you have trouble with this mention it back to me, and I'll look up (on my big PC not my laptop) how I did it. Of course you have to convince you that the error message is really not a real problem.  ***  I've been having a heck of a hard time (in Quartus 16 and 17) generating an example design. In Qsys I select the Low Latency 10G Mac and connect it up to PLLs with the right clock frequencies. Then I click on Generate Example Design. After a long wait I get an error message, and the example design generation fails.  I've also tried to get 10GB Ethernet design examples many different ways (design store, Altera Wiki, etc.) and have not been able to get any example that is usable.  How did you generate a 10GB design example?