simulate DFIFO by using modelsim, outptout ports are zzzz

[Altera_Forum]

I use moselsim SE 10.1a to simulate DFIFO. Quartus ii software version is 12.0. DFIFO has six input ports and three outputs. I give DFIFO six input signals, including aclr, inputdata, rdclk, wrclk, rdreq and wrreq. All they can display correctly in modelsim. But three output ports are zzz,including rdempty, wrfull and output q. The color of three output ports is blue. 

rst is aclr; clk_48M is wrclk;clk_FFT is rdclk; filt_lp_data_i is inputdata;fft_real_in is output data port.  I give the simulation results in attachments column. I have used DFIFO before but I didn't meet this problem. It frustrates me a lot. I hope someone who can help me.

[Altera_Forum]

your wr clk is dead.

[Altera_Forum]

I think I was looking at your rst and thought it was wr clock. is your reset active low or high. Did simulation manage to find fifo model?

[Altera_Forum]

My reset is active low in my system. I know that aclr of DFIFO is active high. So in my code, aclr=~rst. 

How to know that simulation manages to find fifo model? The module ,including FIFO, has been successfully loaded in modelsim. Does it mean that simulation manages to find fifo model?

[Altera_Forum]

If a component model is not found by modelsim it still compiles but when you run simulation it will issue a warning saying fifo is not bound.