Is there a pre-built CXL Type3 example design for DK-DEV-AGI027-RA with CXL IO on the PCIe fingers?
I have built one myself, but I run into cyclic boots under Linux. I was wondering if there is a pre-built and verified sof for this design available to rule out problems with my own build.
Right now I don't know if the problem is with my build or with BIOS settings required by the design.
BTW I have a PCIe build working at Gen5 x16. I also have ASIC based CXL attached memory working on the same host.
