FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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solving Overflow issue in clocked video input module

Honored Contributor II

I am getting overflow and underflow conditions while using (VIP suite) clocked video input and clocked video output modules while working with different input and output clocks. I am using maximum fifo size. different compilations giving different results. I am using Qsys for generating VIP modules. any recommended procedure for getting better and consistant results with VIP suite.

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