FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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some doubts on stratix 10 pcie hard IP ?

Honored Contributor II



In the qsys design. I have ddr3 (512 Mb) and pcie express configured bar0 (pre-fetchable 64-bit memory) and connected to ddr3. 

After generation of .sof file and after programming. when i start the host system and once i type "dmesg" in terminal. it is showing 1 gb memory space (which should be 512mb) configured to bar0. I don't know where i am going wrong . 


Even though , if i proceed further, i am able to access only the first 64mb of entire 512mb space from the host. there is a error print message after running "dmesg" it shows "vmap" virtual memory capacity issue. 


I am very new to something like os, kernal modifications , modifying driver c code.  

Its a great help if someone explains/ clears this issue. 



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