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Honored Contributor I
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strange timing paths in PCIe Gen3x8 AVMM DMA - Arria 10

The design is modified starting from http://www.alterawiki.com/wiki/reference_design:_gen3x8_avmm_dma_-_arria_10 

 

The path below is completely within Altera RTL, which was not modified at all, and does not even have any logic. 

 

It looks like this is because of clock setup or timing constraints. 

 

Any help would be greatly appreciated. 

 

Path# 1: Setup slack is -6.604 (VIOLATED) =============================================================================== +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ; Path Summary +--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ; Property ; Value +--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ; From Node ; top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out.reg ; To Node ; top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_ ; Launch Clock ; top|pcie_a10_hip_0|tx_clkout ; Latch Clock ; top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_ ; Data Arrival Time ; 83.118 ; Data Required Time ; 76.514 ; Slack ; -6.604 (VIOLATED) +--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------+ ; Statistics ; +---------------------------+--------+-------+-------------+------------+-------+-------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +---------------------------+--------+-------+-------------+------------+-------+-------+ ; Setup Relationship ; 0.200 ; ; ; ; ; ; ; Clock Skew ; -3.347 ; ; ; ; ; ; ; Data Delay ; 2.640 ; ; ; ; ; ; ; Number of Logic Levels ; ; 0 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; Clock Network (Lumped) ; ; 1 ; 3.678 ; 100 ; 3.678 ; 3.678 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Cell ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; uTco ; ; 1 ; 2.640 ; 100 ; 2.640 ; 2.640 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; Clock Network (Lumped) ; ; 1 ; 0.331 ; 100 ; 0.331 ; 0.331 ; +---------------------------+--------+-------+-------------+------------+-------+-------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ; Data Arrival Path +----------+---------+----+------+--------+-------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------- ; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element +----------+---------+----+------+--------+-------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------- ; 76.800 ; 76.800 ; ; ; ; ; ; launch edge time ; 80.478 ; 3.678 ; ; ; ; ; ; clock path ; 80.478 ; 3.678 ; R ; ; ; ; ; clock network delay ; 80.478 ; 0.000 ; ; ; 216 ; HSSIGEN3X8PCIEHIP_L0 ; ; top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out.reg ; 83.118 ; 2.640 ; ; ; ; ; ; data path ; 83.118 ; 2.640 ; RR ; uTco ; 1 ; HSSIGEN3X8PCIEHIP_L0 ; ; top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rate7 ; 83.118 ; 0.000 ; RR ; IC ; 3 ; HSSICOMMONPLDPCSINTERFACE_1D5 ; ; top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts.twentynm_xcvr_native ; 83.118 ; 0.000 ; RR ; CELL ; 0 ; HSSI8GTXPCS_1D5 ; ; top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip +----------+---------+----+------+--------+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------
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