stratix hbm2 write request seems pending and blocking read requests to the same address

[ZWang142]

Device: Stratix 10 mx, 1SM16BEU2F55E2VG
*** This problem happens on the real device and cannot be reproduced by simulation yet. ***

HBM Settings: BL8, Controller refreshes all, Autoprecharge FORCED, 256 bits with ECC on

Request sequence:

1- Upon release of reset, sweep the address space and write all 0s to half of the address space interleavely (i.e., write all 0s to 0x0, 0x80, 0x100, 0x180, 0x200, 0x280)

2- (Manually trigger, say 1 min after step 1) Write 4 x 256-bit data consecutively starting at a certain address

3- (Manually trigger, say 1 min after step 2) Read at the same address of step 2

Problem:

The read data of step 3 will not return until another write request is issued to the same hbm  pesudo channel.

Specifically, if issue another write to a different address, and then repeat step 3, then all data are returned on a timely manner. However, if issue another write to the same address as in step 2, then only the data for the first read is returned. If repeat step 3, then the return data is stuck again.

It seems the write request in step 2 is pending, and therefore blocks the read request to the same address (a HBM controller feature to avoid reading stale data???). Another write request to force the previously pending write request, so the blocked read request can return. However, since the 2nd write request will be pending itself, it will again block read requests to the same address.

BTW, I tie awuser and aruser to high to always force auto precharge.

Any help on how to solve this problem? It's driving me crazy. Thanks.

[yoichiK_intel]

Hi

Are you following the correct transaction for write sequence ?  When user request the write access with write address user need to write two clock cycle of write data as attached transaction.

[ZWang142]

Yes, sure, otherwise my simulation will catch it.

Anyway, the problem is gone after I issue another hbm reset (the high active one).