stratix10MX developer Kit HBM2 channel address renge

[貴清水00]

We refer the document UG20031”High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide”.

This IP can have 8 channels max. And can each channel access all HBM address 4GByte?

According to the referenced User guide fig16, the address bus width is 29bit in Byte.

I concern about each channel have an access limit 512MByte .

[NurAida_A_Intel]

Hi,

Thank you for joining this Intel Community.

I am not the HBM2 expert, anyway I will help to check with my colleague regarding this inquiry.

Please allow me some time to check with him and I will update you ASAP.

Thank you for your kind understanding.

Regards,

Aida

[NurAida_A_Intel]

Hi,

Good news! I have an update for you.

The HBM device has 2 type.

• 4GB/4H refers to HBM2 device with a total device density of 4GB in a 4-high Stack,
• 8GB8H refers to a total HBM2 device density of 8GB in an 8-high Stack.

Can you confirm which type are you referring to. Assuming it is 8GB type with 8-high stack:

• In 8GB type, it consist of 8 channel which each channel is divided by two pseudo-channels.
• 8GB is the total capacity of 8 channel. Thus, each channel can support 1GB and each pseudo-channels can support 512MB.

To answer your questions:

1. And can each channel access all HBM address 4GByte? -- No, 4GB is the total density of 4 channels (if you are referring to 4GB4H device type)
2.  I concern about each channel have an access limit 512MByte .-- If this is referring to each pseudo-channels, then yes, it can access limit 512MB.

I sincerely hope this helps.

Thanks.

Regards,

Aida