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Altera_Forum
Honored Contributor I
776 Views

system with DDR2 HPCII can't meet timing requirement!

Hi 

 

In my project, i add a DDR2 HPCII to my system, after compilation, the timming meets my requirement. while after adding a second module to the previous system, the timing no longger meets. The SOPC auto generated module "ddr2_s1_arbitrator" contains critical path.  

 

The device i used is EP3C120F780, and the resource used is 24% after adding the second module. System clock i set is 125MHz, and the second module contains some floating point IPs, like fp_add, fp_div and so on. 

 

Since the module "ddr2_s1_arbitrator" is generated by SOPC system, so what can i do to fix the timing isue? all the auto generated sdc file have been added to the quartus project. 

 

Thanks for your replay!
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2 Replies
Altera_Forum
Honored Contributor I
33 Views

Hello, 

 

I can't give you any answers to your questions, but I face the same problem with the DDR2 HPCII in a SOPC system on ArriaII GX DevKit. In my case it's a violation of hold and recovery times. The critical path lies somewhere in the generated code, to be more precise, the clocks generated by the instantiated PLL within the HPCII. 

 

I tried to use the output of this PLL as system operation frequency, then I added a clock domain crossing bridge between HPCII and remainder of the system, which is driven by another external clock source of the board. In neither version the timing violations were gone. 

 

When I use the DDR2 as instruction and data memory to store NiosII programs, the verification when downloading in Nios IDE reports an error. So, the download of program code must have been broken. Another test involved the "memory test" template program that can be chosen when creating a new project in Nios IDE. I run the program code from on-chip memory so that I can test the DDR2 from a safe point. The memory test routine always fails, apparently there is an issue with the DDR2 timing. 

 

The example program considering DDR2 on the ArriaII GX (from the tutorial section of the "external memory handbook") seems to work. It just uses the ALTMEMPHY with some "example driver", which solely generates write / read bursts. However, I want to build an SOPC builder system, and then I run into then trap. 

 

BTW I added all generated .sdc files to the project to have them processed by TimeQuest Analyzer.  

 

I don't know what to do any more. I am absolutely helpless. I have already walked through tons of material from Altera, but nothing is really useful.
Altera_Forum
Honored Contributor I
33 Views

A pipeline bridge in front of the memory should help. I would recommend skimming through this document to learn more about where to place the bridges especially if you have hooked up a lot of masters to the memory: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf

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