FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

test pattern generator (VIP)

Altera_Forum
Honored Contributor II
1,424 Views

Hello, 

i try to implement a system that displays 

either still color bars for use as a test pattern on a lvds tft panel. 

 

i use a Cyclone IV GX Eval board (EP4CGX150DF31) 

 

my idea is to split the systems in different unit 

 

Test Pattern Generator (VIP) --> Clocked Video Output (VIP) --> lvds serializer --> lvds video target (display) 

 

whereby the lvds serializer already works (i tested it in another design configuration), but test pattern generator makes some problems 

 

for debugging i the place the output signals (of the test pattern generator) to some output pins to check them on a scope, but the compiler reports that these pins stuck at VCC or GND. 

 

can someone explain whats wrong? 

 

best regards 

 

occino 

 

http://i43.tinypic.com/de1vg7.jpg  

 

(http://i43.tinypic.com/de1vg7.jpg

 

http://i43.tinypic.com/25z5rpg.jpg  

 

(http://i43.tinypic.com/25z5rpg.jpg)
0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
177 Views

Is the clock correct? Why You're not using SDI?

Altera_Forum
Honored Contributor II
177 Views

This is just a guess but if you keep reset high then Quartus is free to optimize away all the logic in the test pattern generator and directly tie the outputs to either 1 or 0 depending on their reset state. 

It should work if you connect reset to the correct input pin. Note that for Video IP core the reset signal is active high.
Altera_Forum
Honored Contributor II
177 Views

@Socrates: I think the clock ist correct because its an external clock by a control unit and its exactly the frequency the display expects. 

I don't know this ip core. how can it help me? 

 

@vgs: 

thank you for the hint! i will change it
Altera_Forum
Honored Contributor II
177 Views

the input clock is 27MHz?

Altera_Forum
Honored Contributor II
177 Views

no, its about 84MHz. Its a single channel lvds display with 4 lvds pairs and 1 clock pair

Altera_Forum
Honored Contributor II
177 Views

Well if signals don't toggle, the wrong clock isn't a problem, I suppose. But usually, the clock used in video designs is 27MHz.

Altera_Forum
Honored Contributor II
177 Views

 

--- Quote Start ---  

Hello, 

i try to implement a system that displays 

either still color bars for use as a test pattern on a lvds tft panel. 

 

i use a Cyclone IV GX Eval board (EP4CGX150DF31) 

 

my idea is to split the systems in different unit 

 

Test Pattern Generator (VIP) --> Clocked Video Output (VIP) --> lvds serializer --> lvds video target (display) 

 

whereby the lvds serializer already works (i tested it in another design configuration), but test pattern generator makes some problems 

 

for debugging i the place the output signals (of the test pattern generator) to some output pins to check them on a scope, but the compiler reports that these pins stuck at VCC or GND. 

 

can someone explain whats wrong? 

 

best regards 

 

occino 

 

http://i43.tinypic.com/de1vg7.jpg  

 

(http://i43.tinypic.com/de1vg7.jpg

 

http://i43.tinypic.com/25z5rpg.jpg  

 

(http://i43.tinypic.com/25z5rpg.jpg

--- Quote End ---  

 

 

 

Hi, 

 

I Am working on a similar architecture, I have a LVDS LCD interface, I want to know whether we need to do any bitmapping for LVDS transfers. I have attached a snapshot of required serial data for all 4 channels. Please help me to understand.
Reply