FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

testing sgdma

Honored Contributor II



I met a problem on my way to implement SGDMA transfer complied with PCIe Master/Target core in QSYS system. Without NIOSII, I want to setup the related control registers. My action is simple, to move the on-chip memory to DDR. It seems the whole SGDMA process failed. I am able to write the data through bar in DDR or on-chip memory. I am working in linux with monitor. 


I am working with Cyclone IV GX devkit and with reference design:civgx_qsys_pcie_x4 


I don't know why there is always ''0xDEADDEAD'' in descriptor read register? 

I am curious what to do, which SGDMA registers I have to set? 


Thank you for support!
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