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TGao
Beginner
84 Views

the Pin lead out of IP compiler of PCIE

Hi Sir/Madam,

There is a pin(sim_ltssmstate[4:0]) of IP compiler PCIe in Cyclone V ​,But I can't find in Cyclone IV.

 

Any help would be appreciate !微信图片_20200330170205.png微信图片_20200330170154.png

 

Ted.Gao

0 Kudos
7 Replies
SengKok_L_Intel
Moderator
24 Views

Hi Ted Gao,

 

There are some differences in the simulation PIPE interface between Cyclone IV and Cyclone V. And Yes, the sim_ltssmstate signal is not available for Cyclone IV as the user guide. However, for hardware debug, you can still find the ltssmstate[4:0] from the signal tap.

 

Regards -SK

TGao
Beginner
24 Views

Hi SengKokl, Thanks for your reply, Yes I had find the ltssmstate[4:0] in signal tap, but I also want observe this signal in memory, so I need find this signal in logic Element, so I can connect to my memory interface to collect data. Ted.Gao
SengKok_L_Intel
Moderator
24 Views

For the PCIe AVMM interface, the ltssm signals are not exposed to the top layer. If this is essential for the design, you may manually pull it out from the lower layer.

 

Regards -SK

TGao
Beginner
24 Views

Hi SengKokl, What I need maybe How manually pull it out from lower layer? Ted.Gao
SengKok_L_Intel
Moderator
24 Views

Hi Ted Gao,

 

By referring to the lower layer code, I found that the ltssm is connecting to the test_out bus if the test out width is set to 9 bits. Probably, you can try to use the lower 5 bits of test_out bus.

 

assign test_out_test_out = { pcie_internal_hip_lane_act[3:0], pcie_internal_hip_dl_ltssm[4:0] };

 

Regards -SK

TGao
Beginner
24 Views

Hi SengKokl I will try it ASAP, Thanks for your kindly help! Ted.Gao
SengKok_L_Intel
Moderator
24 Views

I set this forum case to close-pending for now. The status will remain in this state for 15 calendar days, simply post a note in this forum and it will be reopened for further investigation.