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time limited sof file

XXiao2
Novice
‎10-11-2019 03:26 PM
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I am trying to test the LL 10G example and the Quartus generated time limited sof file. Can I use system console to debug this kind of sof file. I am experience some problem with register access: I get master_read_32: Channel closed error every time I access the register in the design.

 

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RichardTanSY_Intel
Employee
‎11-05-2019 06:28 AM
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Could you share the error message?

I am not sure if using the JTAG-to-Avalon Master bridge helps in your case. You can troubleshoot by referring to the link below.

https://www.intel.com/content/www/us/en/programmable/documentation/mwh1411073380259.html#mwh1411073375532

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