timing_violations_onddr3_and_jtag

[SERMASWATHIKA]

Hi Team,

  I have compiled the design which comprises of nios ii , ddr3 and avalon mm other interfaces.

I am getting timing violations. Can you please guide me to resolve this? attached the timing report summary

[sstrell]

https://www.intel.com/content/www/us/en/support/programmable/articles/000092769.html

[TingJiangT_Intel]

Please help to show the violation message in Timing analyzer.

[SERMASWATHIKA]

Hi ,

i am getting negative slack on pll_afi_clock of ddr3 memory

shall i add false path for that violation?

PLease give suggestion

[TingJiangT_Intel]

Is this setup violation or hold violation?

And please using 'report timing' to check and show the path details, thanks.