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töz00
New Contributor I
157 Views

triple speed ethernet on cyclone V E development board

hello, 

i am using Cyclone V E development board which include 5cefa7f31i7n chip and quartus version 15 web edition.

i want to learn how to implement bare TSE IP without nios softcore processor. i want to implement it with VHDL. 

firstly, i generated a TSE IP on QSYS and place it in block and Schematic. I assigned pin numbers and wrote a vhdl which include signals for TSE IP control port signals with using TSE IP USER GUIDE. 

my problem is starting at the control port signals. in the control port signals, there is a waitrequest (reg_busy) signal. it asserts when register read and write access to the TSE and deasserts when their access is completed. 

I controlled these signals with the signal tap analyzer. reg_busy signal is always '1' so i could not write mac_data bits on IP. 

how can i solve this problem or is there any tutorial or hint for implementing bare TSE IP with hardware configuration.  My target is, i only use TSE IP and on chip memory between 2 fpga ethernet port and communicate them in a simple way.

thank you for supports! 

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4 Replies
Deshi_Intel
Moderator
148 Views

Hi,


Reg_busy is status output signal from TSE IP. You should just monitor it instead of controlling it. But your understanding is correct that it should de-assert low when TSE IP is ready to accept user command.


You can refer to either of below reference design to ensure you connect and initialize TSE IP correctly. These are not NIOS II design that should suit your need.


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
148 Views

Hi,


Reg_busy is status output signal from TSE IP. You should just monitor it instead of controlling it. But your understanding is correct that it should de-assert low when TSE IP is ready to accept user command.


You can refer to either of below reference design to ensure you connect and initialize TSE IP correctly. These are not NIOS II design that should suit your need.


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
128 Views

HI,


I didn't hear back from you for some time.


I hope you are doing fine with your project.


For now, I am setting this case to closure. Feel free to post new forum thread if you still have enquiry in future.


Thanks.


Regards,

dlim


töz00
New Contributor I
125 Views

thank you for  all your support.

i have simulated the example design and found the problem. now i am trying to write my control vhdl. 

 

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