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update DDR3 sdram uniphy to Arria 10

dsun01
New Contributor III
1,121 Views

Dear Intel expert, 

I am learning how to use Platform Designer now, I have an EVM design from TI which was in Arria V.  I need to upgrade it to Arria 10(SOC Dev Kit). there are few modules have to update manually, one of it is the DDR3 SDRAM controller,

the error message is 

"Error: mem_if_ddr3_emif_2:DDR3SDRAM Controller with UnPHY Intel FPGA IP is not supported by family Arria 10."

Here is what guess I need to do, 

1. create a new DDR3 or DDR4 IP which is matching for example, the Intel Arria 10 SoC Development. 

2. copy the connection from the old DDR3 module, and delete the old module. 

 

hope I can get some help/direction from expert. 

thank you,

David

 

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12 Replies
sstrell
Honored Contributor III
1,100 Views

Correct.  Arria 10 EMIF architecture is completely different from Arria V.  UniPHY is not used.  Most of the interface is hardened in the I/O in A10.

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dsun01
New Contributor III
1,082 Views

Hi Sstrell

Thank you very much for reply, I know there are lot of examples of the Arria 10 Dev Kit. is there any document/induction about how to update the Uniphy to an A10 interface. just delete the old one and create a new one? is there any special thing need pay attention. 

 

Best Regards,

 

David 

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AdzimZM_Intel
Employee
1,018 Views

Hi Dsun01,

 

Do you have any issue when creating the EMIF IP for Arria 10?

Please let me know later.

 

Thank you Sstrell for providing the info regarding to the Arria 10 EMIF IP.

 

Thanks & Regards,

Adzim

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dsun01
New Contributor III
998 Views

Hi Adzim

Yes,  I am an old FPGA designer, but new to the platform designer. I don't have time to read the user manual of the Platform Designer line by line yet. just hope it is intuitive enough, so I can figure out during the using of it. ( turns out I am not that smart). 

 

In my case, the new device family not support the old IP, in old design approach, the Megacore generate a new core module, I just need to instantiate it in the design( replace the old one). in the new tools I kind of lost after I create a new qsys. It is not clear for me how to replace the old qsys, and make the project linked and compile. I don't think the compiler is so smart that it will make the connection for me. Any way, I am learning how to use the platform designer. I notice that there are lot of example here and there at module level, like PCIe transceiver, EMIF interface to DDR, is there an example/tutorial to show how to link two blocks like PCIe and EMIF together? 

Thanks,

David

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AdzimZM_Intel
Employee
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Hi David,


You can visit Intel Support page to look for the Reference Designs.


Here is the link for the PCIe IP Support Center:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html


For other IPs, you can visit here:

https://www.intel.com/content/www/us/en/programmable/support/support-resources.html


Thanks.

Regards,

Adzim


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dsun01
New Contributor III
903 Views

Hi Adzim

Thank you for the reply, I will check the document in the link, but the way, for the second link, there is a JESD204B Intel FPGA IP link, if you click it.  will show "Server Error!". 

David

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AdzimZM_Intel
Employee
854 Views

Hi David,


Can you try to access the JESD204B IP again?

I think error has been fixed.


Thanks,

Adzim


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dsun01
New Contributor III
844 Views

it didn't work, after a long time struggle, it didn't say "server error“  now, 

 

We're sorry​—​this page
is temporarily unavailable. (Error 500)

We are working to correct the problem. Please try again.
To contact Intel Support, use one of the following options:

 

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AdzimZM_Intel
Employee
821 Views

Hi David,


Do you still unable to access the web?

If yes, then I think you may need to use a different browser.


I've provided the link below.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/jesd204b-support.html


Thanks,

Adzim


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dsun01
New Contributor III
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