using hard IP libraries in cadance simulator

[DChak3]

Hi I have created a project where I used different hard IP's like pcie, nios processor,emif etc. So how can I simulate this IP's in my simulation environment. I have gone through the documents and I found from the tool we can create the libraries and then we can use them in the corresponding simulation environment. So in any case do we need to use the verilog files created by the IP. As quartus doesn't generate filelist. So my question is how we can use this IP' to simulate in our simulation environment. if I am using IP libraries it says some files are missing in the list. But if I am using the IP libraries I am not sure how this error is showing the simulation.

NOTE: if necessary we can provide the simulation environment for debugging purpose.

[RichardTanSY_Intel]

The attached link is a youtube video on how-to simulates using a third party simulator like Cadence.

https://www.youtube.com/watch?v=e0X5KMVt4F8

There is also a simulation user guide in the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-tp-simulation.pdf

Let me know if you need further help.

[DChak3]

Thanks Shyan for replying.

I can able to use hard IP libraries and also able to simulate in cadence.

Now the issue is I saw there is problem with pcie_ptile Avalon st Ip as If i simulate this IP, the simulation stucks in 0.0ns in cadence version use incisive 20.018 .

parameters are gen3x8, 256dp 250mhz.

I tried simulating the example design but there also it shows message as "pcie_ed_tb.dut_pcie_tb.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp.inst.dut.inst.inst.maib_and_tile.z1565a.ctp_tile_encrypted_inst.PROTECTED: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured."

and it stops, its not going further to run the test cases which are included in the example design bfm. example design can be simulate with vcs only.

for simulation i used vcs 2019 version. Ip was generated for stratix10 device 1SD280PT2F55E2VGS1 from quartus 19.4.

[RichardTanSY_Intel]

I have confirmed with the team.

As for now, only VCS simulator is supported for P-tile. Please try VCS instead.

[DChak3]

Hi Shyan

I wonder if this limitation is for the P-Tile example design or for any fpga design that instantiates P-Tile also?

Asking because clearly we have been able to compile and elab the fpga design that includes P-Tile IP using ncsim at past.

[RichardTanSY_Intel]

Yes, this is a limitation for P-tile design.

Perhaps I should clarify by saying that the design can only run through the simulation using VCS.

[DChak3]

So shyan. IF its the limitation, in past we havn't faced this issue if used ptile pcie in our design we tried with cadence only.

Can u confirm if it depends upon version or device. Or this quartus version is not updated to simulate the ptile pcie in cadence. Can we ask direclty to intel FAE. 1. confirming if this is the limitation only for this quartus version ptile pcie or in all versions.

2. If it's so than lets say a design consists of other IP's like emif . nios processor. Than for simulation one is totally dependent on vcs. we cant simulate the entire design in cadence. Dont it seems like becuase of Intel we are also limited to some extent. As all Intel this IP's shall be tool independent.

[DChak3]

Hi one more thing I need to ask. Like in cadence we can create the libraries for hard IP and quartus related macro libraries. Is there is the same way we need to to do for synopsys. How we can create the filelist in vcs setup for hard IP's

[RichardTanSY_Intel]

The user guide below could guide you to simulate the PCIE design example.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf#page=121