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EHait
Novice
239 Views

vid_de signal behavior in HDMI Intel FPGA IP sink (RX)

Hi,

I wander if the vid_de signals (there are 2 of them in Cyclone 10 implementation because the IP outputs 2 pixels at a time.

My question is if the vid_de signals, which are Video Data Enable, behave consistent - always '1' during Active Video time or it may introduce Backpressure by going '0' sometimes?

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3 Replies
Deshi_Intel
Moderator
86 Views

Hi,

 

vid_de is input port to Intel FPGA HDMI IP that indicate active picture region only.

 

This is input port controlled by user logic design and not output port from HDMI IP.

 

If HDMI IP see "1" on vid_de then HDMI will process the data as "active video".

 

Thanks.

 

Regards,

dlim

EHait
Novice
86 Views

hi, Dim., thanx.

 

In the SINK part of HDMI, (the video RX) the vid_de is output from the core .

So the question is if it works as "pixel valid" signal where it may also be invalid in some clock cycles during the "active video" region?

Deshi_Intel
Moderator
86 Views

Hi,

 

Sorry, I am not aware you are referring to HDMI sink.

 

I am not familiar with pixel valid signal.

 

If you look at the next page of HDMI user guide doc (page 102)

 

Are you looking for something like these status signal ?

 

Thanks.

 

Regards,

dlim

 

 

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