FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5987 Discussions

vip clock in and clock out

Altera_Forum
Honored Contributor II
761 Views

In my design for connection with the hd_SDI i am using clkin and clkout (vip) back to back and taking my output and feeding to the hd_SDI ip core . 

 

vedio ==> clkin ip ==> clkout ip ==> hd_SDI(ip) 

data (embedded) (VIP) (VIP)  

 

 

here the issue am facing is am not able to get the output from clkout ip (vip). 

am using 1080i 60 hz. 

 

plz tell me whether my approach is correct or not .
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
84 Views

the clock out vip don't out clock 

you need to insert clock to get the data out 

it is an input clock and not out
Reply