what condition to get JESD204B serial output pin toggling? (it is urgent)

[fxu001]

Hello,

Currently The AV bus can have proper handshake which I can see outxAvstUsrDataInRdy assert, and I return inxAvstUsrDataInValid signal with inxAvstUsrDataIn; however, there is no output toggling present the serial bus outxTxSerialData. When I put in1PatGenEn => '1', there is no serial output signals neither. Can you give me some hints for which condition or setting to generate output signal in serial bus?

Thanks,

-Fred

[Nathan_R_Intel]

Hie, My apologies for the delayed first response. I has a few JESD204B cases and missed this case. To enable the JESD204B IP's Tx out (serial out) to toggle, this are the requirement: i. correct frequency free running reference clock is available to PLL ii. phy and base IP is out of reset iii. calibration or system clock is available to IP iv. Rx issues sync request (sync_n) is asserted. This will transition the Tx into CGS (code group synchronization) state which will cause Tx to transmit idle K28.5 characters which will cause Tx out to toggle. Please check if above requirements are met to generate output signal in serial bus. Regards, Nathan

[fxu001]

Hi Nathan, Thanks your information. When I have further question, I will send you an email again. Thank you so much! -Fred

[Nathan_R_Intel]

Sure Fred,

For more information, you can also refer to our user guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf

Regards,

Nathan