we are trying to simulate(functional) ddr3l controller ip with micron memory model. After reset release, we are able to see PLL lock and memory reset release. we are expecting calibration/initialization of memory starts automatically from the controller after the memory reset release. But we are not seeing any initialization commands from the controller(no toggling on RAS,CASCS,WE). Please help to resolve this.
There is an option in the IP's parameter settings for skipping calibration during simulation to save time. Do you have that option enabled? It is usually recommended because simulating the calibration process can take a loooong time.
we tried all the caliberation types(skip,full and quick) .But in all types ,init_done is not going high .we thought that after initi done only we can initiate read and write operation through Avalon interface.
we also tried read and write through Avalon interface without init_done ..But there is no signal toggling on DDR3 interface . could you please us to resolve this issue .
The IP is not officially support simulation using third party memory model. Have you try run the simulation using the generate example design? The example design is included the generic memory model which validate working with the ddr3l IP.
The intention to ask you try with the example design is to figure out the issue is caused by the simulator or not. I found that using some simulator that incompatible with IP or quartus version, the simulation will stuck after reset release.
I am assuming you are using the UniPHY EMIF in Cyclone V /Arria V/Stratix V device right?
After you generate the example design, you need to use quartus open the generate_sim_example_design.qpf under simulation folder. Then go to tools, tcl scrips... and select generate_sim_verilog(VHDL)_example_design.tcl and run. After the tcl executed, you can see the memory model generate under the submodules folder with name - alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv
When using the example design, actually you do not need to worry about where the memory model located. You can just run the simulation script based on the simulation that you using.
Refer to this chapter to run the example design simulation - 8.2.5. Simulating the Example Design
yes, we are using uniPHY EMIF Arria V device only. whether memory model of example design can be used for our design...how can we use and where can we pick.....does it support micron memory model?we are planning to use micron memory..if not which memory can be supported?
Hello, Micron memory is supported from hardware perspective. However, please double check emif estimator for the memory scheme that you want to use.
At this moment, I will suggest you to purely run the example design simulation and see if it work in your simulator first. You can generate the example design using your targeted micron memory settings - eg. enter all parameters into the IP GUI based on the targeted micron memory, then generate the example design. Follow the step provided earlier and run the simulation.
We are not seeing any ddr initilization / calibration from controller. if ddr controller doesnot support micron mem model in simulation, then we can expect calibration failed, but here there is no toggling on cas ras we cs (for ddr initialization)
We tried with example design and found that it is working(simulation passed).Also we tried to implement the same timing and same memory model(from the example design) for our test environment and found that there is no transactions(initialization) from the controller to memory after memory reset release. Whether any options are there to start the calibration?
if the options is work in example design. Then it should work in your test environment as well. Please check the setup between your environment vs example design.