whether txdatavalid signal should be drivien by mac as 1 or 0 in pcie serdes architecture mode.

[srilakshmi]

Could you please clarify whether  txdatavalid signal should be drivien by mac as 1 or 0 to phy in pcie serdes architecture mode.

as pipe specification  5.1 , architecture diagram 4.2  has also txdatavalid signal . but later in specification it is mentioned that the signal is applicable only in original architecture mode. 

[ventt]

Hi Srilakshmi,

Thanks for reaching out.

May I ask which documentation are you referring to? This will help me to investigate further to provide a precise response to your inquiry.

Based on the PIPE specification in PHY Interface for the PCI Express* (PIPE) Architecture Revision 6.2.1, it is required for the MAC to assert TxDataValid at all times when the PHY is in a mode that does not require the signal.

PHY Interface for the PCI Express* (PIPE) Architecture Revision 6.2.1 Documentation: https://www.intel.com/content/www/us/en/content-details/643108/phy-interface-for-the-pci-express-pcie-sata-usb-3-2-displayport-and-usb4-architectures.html?DocID=643108

Thanks.

Best Regards,

VenTing_Intel

[ventt]

Hi Srilakshmi,

I wish to follow up with you on this forum case.

I hope to hear from you soon so that we can move forward to the next step.

Thanks.

Best Regards,

VenTing_Intel

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[srilakshmi]

Hi  Ven Ting_Intel,

Thank You providing the clarifications. 

I am referring  Revision 6.2 of PHY Interface for the PCI Express*, SATA, USB 3.2, DisplayPort*, and
USB4* Architectures.

it is also mentioned that TxDataValid :: PCI Express mode and SATA mode and USB mode (original
PIPE-only):

I think they mean we no need to take care of TxDataValid  which can mean 0 or 1 also. Could you please clarify about it why we need to drive TxDataValid to 1.

Thanks

Srilakshmi

[ventt · Accepted solution]

Hi Srilakshmi,

Great to hear from you again. It seems like we are looking at the same documentation.

As defined, the TxDataValid signal is to allow the MAC to instruct PHY to ignore the data interface for one clock cycle. Furthermore, the MAC is required to assert TxDataValid (set it to 1) at all times when the PHY is in a mode that does not require the signal.

From the documentation, there are a few situations in which we need to make use of the TxDataValid signal. For instance:

1.Electrical Idle

The MAC should have TxDataValid asserted whenever TxElecIdle toggles. This is because the TxDataValid signal is used as a qualifier for sampling TxElecIdle.

2.128b/130b Encoding and Block Synchronization

For 128b/130b encoding, the MAC must use the TxDataValid signal periodically to allow the PHY to transmit the built-up backlog of data.

To illustrate, let TxData bus = 16-bit wide, PCLK = 500 MHz. Then, for every 8 blocks, the MAC must deassert the TxDataValid signal for one PCLK. This is to allow PHY to transmit the 16-bit backlog of built-up data. The MAC must deassert the TxDataValid signal for one clock cycle immediately after the end of the Nth transmitted block. This means that the TxDataValid must be deasserted for one clock, exactly every N blocks. N can be calculated as follows:

N = 4 for an 8-bit-wide interface if the PIPE interface is operating at 8 GT/s;

N = 8 for a 16-bit-wide interface if the PIPE interface is operating at 16 GT/s.

You may refer to Section 8.19 and Section 8.27 in the documentation for (1) and (2), respectively, for a thorough understanding. I hope this addresses your question well.

Thanks.

Best Regards,

VenTing_Intel

p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate 4/5 for the survey.

[ventt]

Hi Srilakshmi,

I’m glad that your question has been addressed. I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

VenTing_Intel

p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate 4/5 for the survey.