why do I see packets on the user side of the 25G MAC when no fiber is plugged in?

[MWeng3]

If I have no fiber plugged in to the board QSFP28+, I am getting random packets on the user side of the 25G MAC; avalon_st_rx_startofpacket/endofpacket/data etc. with correct looking avalon_st_rx_error bits. I checked our MAC setting and don’t see anything out of place. MAC registers are all default - I do not read/write them. I have used the transceiver toolkit to debug a while ago - to set to Adaptive.

[Deshi_Intel]

HI, Ya, I don't expect Ethernet MAC still generating return data when there is no incoming data traffic anymore. Could it be left over RX data that still haven't been flush out from MAC internal RX FIFO ? It looks me like valid data transfer since you didn't observe error flag on these weird data transaction ? Regards, dlim

[MWeng3]

​I meant that Avalon_rx_st_error bits were set correctly based on the bad data I see coming out  either = x04 or x07   Not left over data in rx fifo as this happens right after power up.  thanks, -mark 

[Deshi_Intel]

Hi Mark, Can you share with me your Ethernet connection setup diagram on how everything is connected to FPGA 25G Ethernet IP ? One suggestion for you is can you try out 25G Ethernet example design to see if you are able to duplicate issue ? This will helps to ensure you have all the correct setting. Other common debug practice will be to ensure FPGA power, clock and reset operation is handle correctly and within spec. Thanks. Regards, dlim

[Deshi_Intel]

The other thing to confirm is you didn't accidentally turn on 25G internal loop back and drive something from TX user logic side, right ?

[MWeng3]

how do I check internal loop back on/off? I checked the TX - nothing going in on the user side. Here is capture from signaltap.

[Deshi_Intel]

HI,

I don't see the st_tx_x ports in the signal tap. Signal tap result is only showing st_rx_x port.

Anyway, you can check for 25G Ethernet user guide doc for internal loopback register control detail.

• For instance, check out page 66 of user guide, table 21 if you are using Arria 10 FPGA else you can search for respective FPGA 25G user guide
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_25gbe.pdf

I can help you better if you shared with me Ethernet connection setup on your board system.

Like wise, pls try out 25G Ethernet example design and also verify FPGA power, clock and reset operation is handle correctly and within spec. (as I suggested earlier)

Thanks.

Regards,

dlim

[MWeng3]

where is design example for 25G Stratix 10? what do you mean "Ethernet connection setup on board system"?

Thanks,

Mark

[MWeng3]

note: this is 25G Ethernet Intel FPGA IP version 19.1 configured MAC+PCS+PMA, enable MAC statistics counters, NPDME enables ref clk 644.531250, enabled auto adaptation triggering for RX CTLE/DFE mode

[Deshi_Intel]

HI Mark, You can generate the example design by clicking "generate example design" button in 25G IP GUI. Below is the doc link for the example design for your reference. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-25gbe.pdf What I meant by "Ethernet connection setup on board system" is if you can draw some high level diagram on how FPGA 25G Ethernet Tx port and RX port is connected to external world then it may help forum community to figure out what's the possible external source that generate the unknown Rx data return. Thanks. Regards, dlim

[MWeng3]

compiled the design example but the .sof errors when loading. I can load the .sof from my design without error. Attached is the board block diagram.

Thanks,

-mark

[Deshi_Intel]

HI mark,

Can you screenshot and show me what's the sof file error message about ?

Did you cross check to ensure you are setting correct FPGA device part number on the example design, modify the design reset, clock pin location to match with your board ?

Thanks.

Regards,

dlim