If I have no fiber plugged in to the board QSFP28+, I am getting random packets on the user side of the 25G MAC; avalon_st_rx_startofpacket/endofpacket/data etc. with correct looking avalon_st_rx_error bits. I checked our MAC setting and don’t see anything out of place. MAC registers are all default - I do not read/write them. I have used the transceiver toolkit to debug a while ago - to set to Adaptive.
I meant that Avalon_rx_st_error bits were set correctly based on the bad data I see coming out either = x04 or x07 Not left over data in rx fifo as this happens right after power up. thanks, -mark
I don't see the st_tx_x ports in the signal tap. Signal tap result is only showing st_rx_x port.
Anyway, you can check for 25G Ethernet user guide doc for internal loopback register control detail.
I can help you better if you shared with me Ethernet connection setup on your board system.
Like wise, pls try out 25G Ethernet example design and also verify FPGA power, clock and reset operation is handle correctly and within spec. (as I suggested earlier)
note: this is 25G Ethernet Intel FPGA IP version 19.1 configured MAC+PCS+PMA, enable MAC statistics counters, NPDME enables ref clk 644.531250, enabled auto adaptation triggering for RX CTLE/DFE mode
Can you screenshot and show me what's the sof file error message about ?
Did you cross check to ensure you are setting correct FPGA device part number on the example design, modify the design reset, clock pin location to match with your board ?