why pcie_tx_st_ready keep low for almost 16384 pcie_clk

[XG_Kang]

My FPGA design sends continueous MWr TLP packets  to CPU module on pcie gen2x4 link。The fpga design use Intel's  Arria10 PCIE HIP 。When sending contineous MWr TLP packets，the tx_st_ready signal of the PCIE HIP will be pulled down for almost 16384 pcie_coreclk cycles sometimes, and will be return to high for ready receiving TLP。Why the tx_st_ready signal be pulled down for so long cycles?how to shorten these low cycles?

[BoonT_Intel · Accepted solution]

Hello Sir,

Probably this is due to the receiver buffer at the host is out of credit limit. I believe the pull-down is expected if you send continuous back-to-back TLP packets.

Maybe you can find a way to increase the frequency of sending updateFC (credit update) packet from the receiver side. 

[BoonT_Intel]

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