It may be the problem of translation. Let me say again, it is the initial configuration and reconfiguration of the device Stratix with the device Cyclone V .Cyclone V as the configuration chip of Stratix 10
Apologize that we do not have the guide for it. If you would like to use AVST programming scheme, it is recommended to have CPLD, processor or MAX 10. The reason is because they boot up fast if compared to FPGA.