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关于Cyclone10LP CRC_ERROR报错问题

客户使用10CL016YUU256I7G,需要CRC_ERROR报错功能,现在出现想象是CRC_ERROR​在配置过程一直为高 ,一直到CONF_DONE拉高后400us左右时间,才拉低。由于使用CRC校验功能,FPGA输出使FPGA重新配置,出现循环状态。FPGA无法正常工作,现在解决办法是通过LC滤波将CRC_ERROR去除,不输出,这样FPGA可以正常工作。Active high signal that indicates that the error detection circuit has

detected errors in the configuration SRAM bits. This pin is optional

and is used when the CRC error detection circuit is enabled.

从这边看CRC_ERROR至高起因是SRAM配置bit出错。为此,想请教一下,是什么原因导致配置过程bit出错,导致CRC_ERROR置高?客户产品需要这个信号判断配置是否出错。谢谢!​

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Employee
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Hi,

 

The CRC_ERROR pin cannot be monitored during configuration process. The CRC_ERROR pin will only be enabled after the configuration process is completed. So I would recommend that your system to ignore the CRC_ERROR pin until CONF_DONE pin is high.

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Partner
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Hi John,

感谢你的回复与支持,谢谢!

在CONF_DONE拉高之前,我们是可以忽略CRC_ERROR拉高的现象,但是CONF_DONE拉高,CRC_ERROR还有400us的高,这样直接影响我使用这个功能了。想问一下,这个CONF_DONE都拉高了,表示配置完成了,为什么CRC_​ERROR还有老高400us呢?导致我们器件逻辑判断配置异常,需要重新配置器件。请问一下,这个是什么原因导致的呢?有什么解决办法吗?谢谢!

Petteryu

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Employee
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Hi,

 

After CONF_DONE is high, it will need 3,192 clock cycles for it to fully enter user mode. So if you would like to avoid the miss detection during the device initialization into usermode then I would recommend you to enable the INIT_DONE pin. So once INIT_DONE pin is high the CRC_ERROR pin will work correctly. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.p... figure 101.

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Partner
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Hi John,

感谢回复,你提的 这个办法可能有用,但是客户产品对安全性要求比较高,能否帮忙分析下CRC_ERROR在配置过程为啥会拉高吗?客户以前有大量使用EP4CE6F17I7N这个料,以前都是判断CRC_ERROR是否拉高判定配置是否有问题。现在10CL016出现这种情况,现在客户想了解的是出现这个现象的原因​?还有与设计有没有关系?客户做的是工业安全产品,对异常现象没有合理的解释,客户不会接受的。您说的方法,可以作为应急方法使用。谢谢!

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Employee
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Hi,

 

During the configuration mode, CRC_ERROR pin is not enabled yet and this is pin is a dual-purpose pin so it it set to tri-state with weak-pull up. The design will only start to work when it enter usermode. When it is in standby or configuration mode, the all normal pin is in tri-state with weak-pull up. This is to avoid any miss detection by external device.

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Partner
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Hi,

CRC_ERROR在双功能引脚,但是没有在dual—purpose引脚里面可以设置tri-state with weak-pull up?只有CRC_ERROR使能引脚?详见附件。

还有一个疑问,您说在INIT_DONE置高以后,才进入用户模式,在CONF_DONE拉高以后,还有3192时钟周期后才进入用户模式,理论上按照100MHz,3192*100M=31.92us,10Mhz,3192*10M=319.2us,也就是说,CONF_DONE拉​高,400us应该已经进入用户模式,这个是CRC_ERROR就表明已经配置完成,进入用户模式了又发生了CRC_ERROR报错,原因还是SRAM的吗?或者您说的3192时钟进入完全用户模式,那么这个时钟周期是多少呢?

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Partner
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Hi,

还有我的理解是CRC_ERROR使能打开,我的理解是在配置过程如果有失败,应该CRC_ERROR应该就会拉高的,我的理解是不需要进入用户模式?不知道我的理解是否正确?谢谢!​

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Employee
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Hi,

 

Sorry for the confusion on the CRC_ERROR pin. The CRC_ERROR pin is an optional pin where when it is disable then it will be tri-state with weak-pull up. During configuration, if there is any CRC error then the configuration will failed and nStatus will be triggered. The CRC_ERROR pin will only be used to monitor the SEU during usermode. The pin cannot be used during configuration.

 

The device will need at least 3192 clock cycle for it to enter usermode.

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Partner
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Hi ,

请问一下,这个at least 3192 clock cycle 中clock cycle 是哪个时钟?是FPGA外部时钟源的主时钟?还是FPGA内部时钟?时钟周期是多少?请帮忙告知,谢谢!

 

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Employee
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Hi,

 

Default it will be related to the internal oscilator except that if your design is using clkuser pin for configuration then user need to make sure to provide additional 3192 clock after CONF_DONE is high.

 

In other words, if you are using internal clock this number is not important and user will need to monitor the INIT_DONE pin to make sure that it is already in usermode.

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Partner
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Hi,

CRC_ERROR工作模式和过程,我现在了解了。有个问题需要请教。客户使用Cyclone10LP,工作一年半了,现在用户模式下出现CRC_ERROR查看了解可能原因是singleevent

upset (SEU) or soft errors,我们如何确认这个原因?还有我们如何去解决这个报错现象?有什么措施,我们来防止这个因为SEU或者Soft error而影响的问题?谢谢!

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Employee
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Hi,

 

Just would like to confirm, you would like to understand if the SEU is happening on critical bit or not right? If yes, then I would recommend you to implement Advanced SEU features (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altadvseu.pdf) to confirm if the failure is critical or not.

 

When CRC_ERROR happen then it is always a real SEU happening as the configuration will always performed check on the CRAM bit.

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Partner
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Hi,

感谢!

客户使用的是MAX10和Cyclone10LP,这种低端器件,而你链接提供的Avanced SEU IP只能支持Arria10,Cyclone10GX,Stratix V,Arria V,Cyclone V,Stratix IV,Arria II GX/GZ。目前看不能支持客户现有的器件。客户使用的器件从handbook看,出现这种CRC_ERROR报错原因一个是SEU,一个software error。目前看客户工作的环境是工业环境,也不是特别恶劣,不能确定是SEU产生的,但是software error也不知如何定位?所以想向您确认一下,出现这种现象的原因,我们如何去定位?还有,客户这种现象不能经常复现?我们如何去定位?还有出现这种现象,我们如何应对,我们如何在设计中防止这种现象?或者预防这种效果?谢谢!

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Employee
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Hi,

 

Sorry for the confusion. We do not support Advanced SEU features in Cyclone 10 LP device. If you would like to use Advanced SEU device then you will need to migrate your device to Cyclone V or Cyclone 10 GX device. Sorry for the inconvenience.

 

For Cyclone 10 LP, we can only detect if CRC is happening or not and not able to further isolate if the error is happening on the critical bit location or not.

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