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在用7.2版本进行时序约束的时候,写好的SDC文件在全局编译的情况下始终会报错;其报错内容为:
1,Critical Warning: Read_sdc failed due to errors in the SDC file
2,Error: wrong # args: should be source fileName while executing source -rsrc itcl (uplevel body line 1) invoked from within uplevel #0 source -rsrc itcl
针对这个问题做过一些尝试:
- 简化SDC内容,仅在其中加一个FPGA的输入时钟约束甚至清空SDC的内容;编译时仍然报这个错;
- 把工程在7.1版本中打开,同时生成一个SDC文件并加载编译,没有编译报错;
- 在7.2工程中删除SDC文件,然后clean project,之后再加入SDC文件,再编译时还是这个错误;
- 由于使用的project是之前同事编译好的project的QAR压缩版解压;我在原版解压后编译任何SDC不报错,但是在我进行任何代码的更改之后再编译SDC会报错。
关于这个报错,请问有什么建议吗?谢谢
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Hi,
Could you share both the working and non-working sdc file?
Thanks.
Best regards,
KhaiY
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Hi,
I could not find the attachment in this forum thread. Could you please reattach?
Thanks.
Best regards,
KhaiY
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Hi,
The sdc file looks good. Could you share the full error message including the submessages?
Thanks.
Best regards,
KhaiY
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Hi,
This might be the reason. Since customer can compile the design after creating a new sdc, I suggest customer to continue using the new sdc. If customer faces any problem with the new sdc, please provide the design for investigation. I can help to compile in the latest version of the software and see if the problem persists.
Thanks.
Best regards,
KhaiY

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