FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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请问，FPGA的差分ClK引脚，p管脚用作单端时钟输入或输出了，n管脚可否用作普通I/O，还是必须空着？如果不用空着，是否需要接地？谢谢

smeng12
Partner
‎03-30-2020 02:02 AM
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YuanLi_S_Intel
Employee
‎03-31-2020 03:22 AM
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你好，n 是可​用作普通I/O的。如果没用，可以空着，因为里面会pull up。

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